| Resolution (bits) | Throughput (Sps) | Integral Linearity (%FS) | Differential Linearity (±LSB) | Dynamic Range (dB) | Power Consumption (mW) | Package |
|---|---|---|---|---|---|---|
| CS5012A | ||||||
| 12 | 100 | 0.0060 % | 0.25 | 73 | 150 | 40 PDIP 44 PLCC |
| CS5014 | ||||||
| 14 | 56 | 0.0020 % | 0.25 | 83 | 150 | 40 PDIP 44 PLCC |
| CS5016 | ||||||
| 16 | 50 | 0.0010 % | NMC | 92 | 150 | 40 PDIP 44 PLCC |
The CS5012A/14/16 family of 12-, 14- and 16-bit monolithic analog-to-digital (A/D) converters have conversion times of 7.20 µs, 14.25 µs and 16.25 µs, respectively. Unique self-calibration circuitry ensures excellent linearity and differential non-linearity, with no missing codes. Offset and full-scale errors are kept within 1/2 LSB (CS5012A/14) and 1 LSB (CS5016), eliminating the need for calibration. Unipolar and bipolar input ranges are digitally selectable.
The pin-compatible CS5012A/14/16 family members each consist of a digital-to-analog converter, conversion and calibration microcontroller, oscillator, comparator, microprocessor-compatible 3-state I/O and calibration circuitry. The input track-and-hold, inherent to the sampling architecture, acquires the input signal after each conversion using a fast slewing on-chip buffer amplifier. This allows throughput rates up to 100 kHz (CS5012A), 56 kHz (CS5014) and 50 kHz (CS5016).
An evaluation board (CDB5012/14/16) is available, which allows for fast evaluation of A/D converter performance.

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