Product News

CS61584A

3.3 V and 5 V Dual T1/E1 Line Interface Unit


Power Supply (V)Control ModesLine CodersNumber of ChannelsTBR-12 CompliantImpedance Matching Line DriverArbitrary Waveform OptionPackage
3.3 or 5 Host & H/W AMI, B8ZS & HDB3 2 68 PLCC
64 TQFP
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The CS61584A is a dual line interface for T1/E1 applications, designed for high-volume cards where low power and high density are required. The device is optimized for flexible microprocessor control through a serial or parallel host mode interface. Hardware mode operation is also available.

Matched-impedance drivers reduce power consumption and provide substantial transmitter return loss. The transmitter pulse shapes are customizable to allow non-standard line loads. Crystal-less jitter attenuation complies with most stringent standards. Support of JTAG boundary scan enhances system testability and reliability.


  • Crystal-less jitter attenuator meets European CTR 12 and ETSI ETS 300 011 specifications
  • Matched-impedance transmit drivers
  • Transmitter High-Z capability
  • Common transmit and receive transformers for all modes
  • Serial and parallel host mode operation
  • User-customizable pulse shapes
  • Supports JTAG boundary scan
  • Compliant with
    • ITU-T Recommendations: G.703, G.704, G.706, G.732, G.775 and I.431
    • ANSI: T1.102, T1.105, T1.403, T1.408, and T1.231
    • FCC Rules and Regulations: Part 68 and Part 15
    • AT&T Publication 62411
    • ETSI ETS 300 011, 300 233, CTR 12, TBR 13
    • TR-NET-00499
  • 3.3 V and 5 V versions
  • Package: 68-pin PLCC, 64-pin TQFP; lead-free assembly

CS61584A

3.3 V and 5 V Dual T1/E1 Line Interface Unit

Overview

Power Supply (V)Control ModesLine CodersNumber of ChannelsTBR-12 CompliantImpedance Matching Line DriverArbitrary Waveform OptionPackage
3.3 or 5 Host & H/W AMI, B8ZS & HDB3 2 68 PLCC
64 TQFP

Description

The CS61584A is a dual line interface for T1/E1 applications, designed for high-volume cards where low power and high density are required. The device is optimized for flexible microprocessor control through a serial or parallel host mode interface. Hardware mode operation is also available.

Matched-impedance drivers reduce power consumption and provide substantial transmitter return loss. The transmitter pulse shapes are customizable to allow non-standard line loads. Crystal-less jitter attenuation complies with most stringent standards. Support of JTAG boundary scan enhances system testability and reliability.

Features

Diagram

CS61584A Product Diagram

Related Documents

 
 

Design Resources


Tools and Software

 

Product News

  • Mar 29, 1999
    Cirrus Logic Enables Higher Telecommunications Line Densities with Smallest Full Featured T1/E1 Line Interface Unit
    New Crystal Mixed-Signal Chip Is Industry's Only 3.3V Multi-Port T1/E1 LIU to Meet Stringent CTR-12 Jitter Attenuation Spec
  •